The present invention relates to a test circuit for a watch integrated circuit which drives a liquid crystal in a multiplex mode.
Conventionally, an integrated circuit for driving a liquid crystal in a multiplex mode produces at least three voltage values at predetermined timings to drive the liquid crystal divisionally.
FIG. 1 shows a display pattern diagram of a liquid crystal dot matrix display, in which common electrodes (COM1-COM6) are arranged in the lateral direction, and signal lines are arranged in the longitudinal direction. Cross points of the lateral and longitudinal signal lines are driven time-divisionally in response to drive-timings of the common electrodes.
FIG. 2 shows a waveform chart of a multiplex drive mode in FIG. 1.
In a multi-divisional drive (six division in the case of FIG. 1), generally, at least three voltage values are applied to the liquid crystal alternately at preselected drive timings to drive the common electrodes. Namely, since plural display picture elements should be controlled by one signal line, voltages such as 0 V, -1.5 V, -3 V and -4.5 V should be applied to show the contrast of the liquid crystal vividly and to eliminate cross talk. An example of the drive waveform to realize the display condition in FIG. 1 is shown in FIG. 2, in which the voltage level at the drive timing indicated by the oblique line hatching is the effective drive level of the common electrodes, and the voltage level at the drive timing indicated by the dotted hatching is the effective drive level of the signal lines.
The phrase "effective drive level" means the level which satisfies the condition to illuminate (darken) the liquid crystal. The effective drive levels of the common electrodes are produced in turn in accordance with the drive timings of the electrodes COM1-COM6 as shown in FIG. 2.
The signal lines take the largest potential difference level (-4.5 V in FIG. 2) relative to the electrodes COM in case the liquid crystal is turned on and illuminated, while they take the smallest potential difference (-1.5 V in FIG. 2) in case the liquid crystal is turned off.
When the logical test (level "1" or "0") of the watch integrated circuit to turn on or off the liquid crystal is carried out to display the liquid crystal in a dot matrix mode, the test terminals of the LSI tester are switched ON and an output from the integrated circuit is judged by the LSI tester. As known in the art, the term "LSI tester" refers to test circuitry incorporated in the integrated circuit by the LSI maker for use in testing the operation of the integrated circuit.
FIG. 4 shows an embodiment of a watch integrated circuit in conjunction with an LSI tester. Reference numeral 41 denotes a comparator which comprises the LSI tester, and 42 denotes a watch integrated circuit. The output from the watch integrated circuit, i.e., the outputs from the common electrodes COM1-COM6, is judged by the comparator 41 of the LSI tester. Since the LSI tester presently used is for testing the logical circuit, the judging level is "1" or "0". Namely, the tester judges the level "1" if the voltage is less than -4.3 V.
In the testing method illustrated above, however, the LSI tester cannot judge the logical level when the voltage levels are -1.5 V and -3 V.